The present invention relates to a semiconductor memory and a read method of the same and, more particularly, to an FBC (Floating Body Cell) memory formed on an SOI (Silicon On Insulator) substrate and a read method of the same.
(1) Structure of FBC Memory
The FBC memory is an n-type MOSFET formed on an SOI substrate. An outline of the structure of the FBC memory will be described below. A memory cell has the four types of electrodes described below:
1) Word line: A word line is driven to select a memory cell in read and write operations, and corresponds to the gate electrode of a MOSFET of the memory cell. A gate voltage Vg is applied to the word line.
2) Bit line: A bit line applies an appropriate bias voltage to the memory cell in read and write operations, and is used to input and output data. The bit line corresponds to the drain electrode of the MOSFET of the memory cell. A drain voltage Vd is applied to the bit line.3) Source line: A source line corresponds to the source electrode of the MOSFET of the memory cell. A ground voltage VSS is applied to the source line.4) Plate line: A plate line is an electrode formed on the lower surface of a box oxide film of the SOI substrate. This electrode is a counterelectrode of a body region in a floating state of the MOSFET of the memory cell.(2) Operation of FBC Memory
The operation of the FBC memory having the above structure will be explained below.
1) Write of Data “1”
The n-type MOSFET of the memory cell is operated in a saturation region by biasing the cell to drain voltage Vd=2 V and gate voltage Vg=1.5 V. Consequently, an impact ionization phenomenon occurs at the drain end of the memory cell to generate hot carriers. The body region of the memory cell stores the generated holes. When the body region thus stores the holes, the body effect makes the threshold voltage (letting Vth1 be the threshold voltage when data “1” is held in the memory cell) of the MOSFET lower than a normal threshold voltage.
Note that in a bulk MOSFET, holes generated by the impact ionization phenomenon are absorbed from the substrate via well contacts and hence are not stored in a memory cell, unlike in the memory cell of the FBC memory.
2) Write of Data “0”
The p-n junction at the drain end of the memory cell is biased in the forward direction by biasing the cell to drain voltage Vd=−1.5 V and gate voltage Vg=1.5 V. Since this draws the holes stored in the body region to the drain side, the potential of the boy region deepens, so the threshold voltage (letting Vth0 be the threshold voltage when data “0” is held in the memory cell) rises.
3) Data Read
The memory cell is operated in a linear region by biasing it to drain voltage Vd=0.2 V and gate voltage Vg=1.5 V. The difference between the potentials of the body region resulting from the difference between written data is read out as a difference between the threshold voltages Vth1 and Vth0. The foregoing are the biasing conditions of the operation of the FBC memory cell.
(3) Characteristics of FBC Memory
The FBC memory performs a data read operation in the linear region. Therefore, it is conventionally assumed that a signal in the body region does not deteriorate. In practice, however, carriers stored in the body region reduce owing to a phenomenon called charge pumping.
This phenomenon is that if a word line of a memory cell in which holes are stored in the body region because data “1” is written is accessed a plurality of number of times, the holes are trapped by the interface state of the interface between a silicon oxide film and silicon substrate, and the data “1” changes to data “0”. This phenomenon makes the FBC memory require a restore operation.
The problem of the linear operation of the MOSFET as the FBC memory cell will be described below.
A drain current Id of the MOSFET operating in the linear region is given byId=K(Vg−Vth−½×Vd)×Vd  (1)
On the other hand, the drain current Id of the MOSFET operating in the saturation region is given byId=K(Vg−Vth)2  (2)
where K is an amount depending on the basic parameters (e.g., the gate length, gate width, and gate oxide film thickness) of the device.
As is obvious from a comparison of equation (1) with equation (2), the drain current Id is independent of the drain voltage Vd in the saturation region operation, and depends upon the drain voltage Vd in the linear region operation.
When the drain current Id depends upon the drain voltage Vd, the parasitic resistance (channel resistance Rch+drain resistance Rd+source resistance Rs) of the MOSFET increases the variation in drain current Id. This is so because in the linear region operation, the drain current Id is readily influenced by the parasitic resistance (drain resistance Rd+source resistance Rs) except for the channel resistance Rch.
On the other hand, in the saturation region operation, the drain current Id is independent of the drain voltage Vd, so the ratio of the channel resistance Rch in the total parasitic resistance increases.
Data read from the memory cell of the FBC memory is performed by reading out the potential difference in the body region as the difference between the threshold voltages Vth1 and Vth0. In practice, however, the threshold voltages Vth1 and Vth0 cannot be directly read out. Therefore, the drain current Id corresponding to each threshold voltage is read out.
In the conventional FBC memory as described above, the potential difference in the body region is read out as the difference between the drain currents Id in the linear region operation. Since this superposes the variation in parasitic resistance on the variation in drain current Id, an operation error occurs during data read and decreases the yield.
A reference concerning the conventional FBC memory is:
Japanese Patent Laid-Open No. 2002-246571